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BACKEND DESIGN ENGINEERS

analog circuit design digital IC design physical verification back-end tools and designCadence DFII CadenceDLE and IC craftsmen Design compiler (synopsys) schematics,simulation, layouting,SP & R Cadence Silicon Ensemble, Design PlannerIC-Craftsman, Pearl, Virtuoso, Spectre or Avant! Aquarius,Apollo, Planet-PL ·Cadence Dracula, Diva Assura or Mentor Calibre or Avant!Hercules Cadence HyperExtract, Avant! Star-RC, Arcadia

QA Engineer Backend Automation
Position Summary
Lead the quality assurance efforts for several of our enterprise product offerings
Write and maintain test plans and test cases to verify back-end applications
Independently create and owns methods to verify and approve newly developed or modified backend component and systems
. Develops and owns test plans, harnesses and test cases and execution including results analysis, cause identification, and reporting.
Develops back end automation using php, perl, bash and sql, which can be leveraged for performance testing and regression testing.
Investigates test database details and recommends ways to improve product functionality, usability, reliability performance and scalability.
Works independently using engineering practices to evaluate enhance and maintain existing quality methods & processes.
Qualifications:
A Bachelors degree in Computer Engineering, Computer Science.
A minimum of five (5) years experience as a Software Test and Quality Control/Assurance Engineer on large scale software systems, applications or computer systems.
Understanding of an SaaS / ASP environment.
Proficiency writing and executing Internet technology test plans (including HTTP, HTTPS and TCP/IP) that support webbased, client facing applications.
Specific QA/QC expertise and experience with load and performance testing back end components required.
Demonstrated knowledge and application of engineering concepts and skills required.
Direct experience in computer programming, scripting and software development required.
Proficient with these technologies:
Unix Linux Bash Perl Scripting PHP, JavaScript & HTML Windows Platforms PHP White box testing

Physical design engineer
Description
Creates bottoms up elements of chip design including but not limited to: cell, and block level custom layouts, FUB level floor plans, abstract view generation, RC extraction, and schematic to layout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, custom polygon editing, auto-place and route algorithms, floor planning, full-chip assembly, packaging, and verification. Troubleshoots design issues and applies proactive intervention. May schedule staffing, execution, and verification of complex chips development and execution of project methodologies and/or flow developments. Must possess the skills to take a block through the backend flow and achieve timing and verification closure. Must be able to work standalone as well as work with others to accomplish block closure.
Qualifications
Minimum requirements: Education: BS in Electrical Engineering
Skills: 3 years using perl and tcl scripting language
Experience: Minimum 7 years experience in physical design related activities including backend APR work using ICC, primetime, and hercules. Must be able to debug timing violations, clock tree latency and clean drc violations.

Physical design engineer analyst
Preferred requirements: MS in Electrical Engineering
2 years experience analyzing RV, SI, and EM results

Physical Design Engineer with First Encounter
Experience : 3 to 7 yrs
Tools: Cadence, First encounter, Celtic, voltage storm, PKS, Calibre DRC and LVS
HI SPEED CLOCK PHYSICAL DESIGN ENGINEER
Description
HIGH SPEED CLOCK PHYSICAL DESIGN ENGINEER
RESPONSIBILITIES:
Responsible for specifying, implementing and verifying the high-speed clock physical design on digital vlsi chips
Participate in global digital circuit design team
Interface with analog designers and clock architects to ensure clock distribution meets functional, reliability and timing targets.
Interface with dft and bringup teams to ensure robust design-for-debug
MINIMUM REQUIREMENTS:
Masters Degree in Electrical Electronics and 7+ years circuit design experience on large high speed digital vlsi chips
High-speed cmos circuit design expertise, full-custom, static and dynamic logic, full-chip, datapath and cell level.
Solid lead design experience, demonstrating excellent engineering judgment.
Solid knowledge of deep submicron process and circuit design issues, design for manufacturability and reliability issues
Expertise in backend chip design flows, tools and overall methodologies, chip integration, library cells, lvs, drc.
Able to communicate clearly and effectively, ability to work effectively in a production environment, with enthusiasm and positive energy

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analog circuit design digital IC design physical verification back-end tools and design Cadence DF II Cadence DLE and IC craftsmen Design compiler (synopsys) schematics, simulation, layouting, SP & R Cadence Silicon Ensemble, Design Planner IC-Craftsman, Pearl, Virtuoso, Spectre or Avant! Aquarius, Apollo, Planet-PL ·Cadence Dracula, Diva Assura or Mentor Calibre or Avant! Hercules Cadence HyperExtract, Avant! Star-RC, Arcadia